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    "topic": "Welcome to [wafer.space](https://wafer.space/) - \ndocumentation at [wafer.space github](https://github.com/wafer-space) - \nbuy at [buy.wafer.space](https://buy.wafer.space) - \narchives at [discord.wafer.space](https://discord.wafer.space/)"
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      "content": "quick sanity check before I submit - Should I set the ID to something that's unlikely to clash?",
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      "content": "or is that set wafer.space side when the precheck is run?",
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      "content": "The precheck does not check it against the other IDs, but the platform should prevent you from choosing an existing ID. The precheck will update the ID macros in your design with your chosen ID.",
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      "content": "ah, cool.",
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      "content": "thank you",
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      "content": "@Tim 'mithro' Ansell When is the next shuttle run scheduled?",
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      "content": "I suspect a few weeks after this run has been delivered so people can examine a design and submit an updated version",
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      "content": "so  about 2 weeks after Early Q4 2026     Bare dies and packaged parts shipped to customers",
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      "content": "Well at some point runs should be overlapping.",
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      "content": "Okay, the color NTSC signal generator is coming along *really* well. It looks like I will be able to generate all the colors, just really badly.",
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      "content": "I\u2019m also going to attempt PAL again, but expect that one to catastrophically break again",
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      "content": "just adapt one of the demo's that looks good and has a friendly license to your modulator's digital interface?",
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      "content": "Not really a thing since a RGB to YIQ converter would be too many gates, I think",
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      "content": "just check it runs at less or equal resolution vs. your modulator's needs, and black box it as necessary",
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      "content": "ehhhh",
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      "content": "Oops, took me until now to get a repo going\nhttps://github.com/AvalonSemiconductors/ws-submission-2026",
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      "content": "The functional components are actually done, leaving me with a comfortable two weeks to get the art ready. There is a block of free space on the die reserved for it.",
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      "content": "@Tim 'mithro' Ansell This is the project I wish to use to officially test my SCL, as well as my multi-project setup using my SCL. I\u2019m also using the level-shifting IO pads, but for having a 5V IO voltage and 3.3V core voltage, which should be interesting. Also has layouts generated by my custom flow tool, *analog* layouts meant for 3.3V operation and, of course, a bunch of CPUs.\nHoping to get a lot of mileage out of this one when it comes to testing things.",
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      "content": "Nice setup",
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      "content": "I fixed the antenna violations so.... I\u2019m actually done way ahead of deadline for once. This is highly unusual!",
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      "content": "I\u2019m just waiting for the art now",
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      "content": "I guess I\u2019ll just sit here and wait for two weeks, then go get waffles?",
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      "content": "In case you're bored, a mux4 would be a great addition to your SCL \ud83d\ude09",
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      "content": "is that in a repo?  Ste ps1 guy loves color bars, loves analog and vga.  might want to see what you are doing.",
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      "content": "oh look, a repo appeared!",
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      "content": "We will see. I am burnt out right now.",
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      "content": "In your position I'd think scripting together a flow of minting a _lot_ of `.nodeset`'s to cover all multistable/regenerative-feedback node voltages,\n - through probably the LVS tooling\n - and some minor singled-out-cell pseudo-DC-op-point sims where you'd start the transient with the regular DC op point initialization as always, then throw whatever waveforms against the inputs that are needed to bring the internal state into the target state, then just stop imposing a maximum step size and let the time integrator run for like an entire simulated minute or so, to then harvest the final state's node voltages from it (for the correct PVT corner! If it's _too_ different one would risk the nonlinear solver potentially skipping across the forbidden band and deciding the flip-flop is actually better off in the opposite state; I do _think_ in principle this could be solved by using the advanced continuation functionality:\nthe attached user guide's \"Figure 8-3\" \"manual replication of MOSFET contonuation\", amended with a 3rd `conparam` entry that happens after the `mosfet:gainscale` and `mosfet:nltermscale` entries, which will be essentially the output conductance of the current-type `B`-source which hard-forces the stateful digital logic cell's internal node voltage to the reference DC static voltage _of the desired internal state of that particular cell,_ and is ramped from a very high conductance (strong but still sufficciently numerically behaved especially when it comes to transitioning out of the forced state; I'd probably just start with `1 siemens` for any vaguely normal CMOS SCL internal nodes) down to literally `0` (which will have it be open-circuit at transient sim runtime). The parameter names legal to put into `conparam` are the same ones that are also legal to `.STEP` (the docs for how to casually do `.STEP` are far far easier to approach/read/understand than the fancy continuation stuffs).\n`.options loca stepper=1 predictor=1 stepcontrol=1` could be semi-necessary to (properly/reliably) handle the effects of combinatorial loops through the (non-transparent at the time of the continuation solving!) flip-flops; if the continuation DC OP point solve ahead of the transient sim itself takes too long it'd be worth testing whether it's sufficciently robust with the tangent predictor `0` and thus the downgrade from the arc-length continuation `stepper=1` to `stepper=0`.\nThough I guess _maybe_ it has to do continuation over the output resistance and push that out to near-infinity in the continuation solve process (default is like `100 exa`); the specified parameter constant value applicable outside of the special circumstances in which the `LOCA` does continuation on it, will need to be a sentinel (I'd suggest exact `0` or \"anything negative\"), as it shall be as non-interacting and as sparsified-away by the linear solver and all as possible (||it's not a problem because the discintinuity doesn't happen while a non-linear solver tries to solve the system of equations and could have called the behavioral function with node voltages/branch currents far from anythign physical, because that's just discintinuos in a parameter, and that parameter doesn't change during any transient time integration...||).\n\nOverall the idea I'm proposing is to use gate-level digital sim (post-techmapping (and any retiming and other such intrusive changes to the logic) verilog-sim basically \ud83d\ude04 ) to fast-forward to an interesting moment, snapshot all stateful state, map that against pre-computed DC op points of the cell library, use the LVS matching provisions to match that state to post-PEX SPICE node identifiers, emit a spice file to-be-`.include`'d full of those continuation-capable cell's-internal-node-forcing B-sources (test if things are faster when forcing combinatorial nets as well, or if the additional effort expended negates the faster convergence; `.nodeset` is likely cheaper for those though it's just not reliable), and start the `.tran` sim.",
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      "content": "(I can help later next week on the matter if you want; I'm just not at all deep enough int the digital simulation and LVS tooling side to handle that side of this simulation-type-marriage.)",
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      "content": "Goal IMO would be to (1) test some particularly questionable timing paths that came up in static timing analysis, (2) check if interaction between digital and analog aspects behaves sufficiently well/nicely to not be concerned about mixed-signal features being DOA due to oversights in the analog/digital interface specs, and (3) sanity check that at least normal interaction with any of the non-SCL parts of the chip (_any_ of those) shows no signs of anythign shorting out or being close enough to shorting out to be nearly-equivalent.\n\n(I'm still mildy traumatized by how you (not-)handled the excessive current draw/heating of the Run1 die's DAC's buffers.)\n\n(The glitching of the video signal you've blamed on the lack of latching of the digital feed to the DACs is actually something I'd file under the above mentioned reason number 2, as it's one thing to accept the glitching if one is aware of it, but a whole nother thing to not have expected it/thought about it being possibly an issue.)\n\n(I'm not sure but depending on what you spit out of the NTSC modulator, like in theory there is place for the audio carrier, parts of the functionality are contingent on non-terrible artifacts/interference behavior, as e.g. audio will eventually hurt or at least give headaches if it's bad enough with some artifacts at least.)",
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      "content": "forgot to attach the file",
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      "content": "I apologize for being _this_ late to realize",
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      "content": "(that the state of the tooling outside magic is beyond questionable, as it's arguably unacceptable.... it's HORRIBLE do target with klayout unles sone sticks to digital SCL only, and even there tholin knows all too well how not-tuned the tooling is to deal with this process..... _antenna violations!_)",
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      "content": "....I guess the teapeout deadline there has now since _really_ taken hold/cemented itself as final",
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      "content": "I actually have a single unused pad on my die. How unusual.",
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      "content": "Probably needs to a PR to nix-eda, we don't support this.",
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      "content": "Taking a closer look, you only seem to 3 major semver versions behind - so that might be a start",
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      "content": "yay!",
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      "content": "Not gonna do too many runs. I have to do manual edits to the GDSII file each time.",
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      "content": "it can be near the edge - short and only sacrifices a few working die",
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      "content": "for imaging attempts.",
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      "content": "also: if someone can use some of their unused area for some large blobs so that we have an easy target to slice into",
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      "content": "regardless of how we cut the die",
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      "content": "There are plenty of unusable die near the edges. still whole size, but creep into the exclusion zone",
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      "content": "do you have a image of the cut pattern?",
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      "content": "either run - or even a fictional run",
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      "content": "next run",
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      "content": "fine for me to scribble conctpt art :p",
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      "content": "assuming we can get one bonus cut on only one wafer, then one or more of those can add some ... shapes?  that the cut will slice",
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      "content": "given the timeline, don't need to wait for cut confirmation - just shove the shapes into existing design and maybe something will happen",
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      "content": "what are you hoping to get from this? you just would get a bunch more half height dies?",
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      "content": "image it in Peter's SEM",
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      "content": "why not just let me give you some of the scrap ones?",
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      "content": "this cut will destroy whatever.  but I'm assming it will be a nice clean cut.  not sure how else to get an edge view",
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      "content": "how do we cut?",
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      "content": "Ah, I see. you're looking for a cross section of active silicon, not just in the kerf",
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      "content": "there are a number of test features that GF puts in the middle of the reticles (the blank spaces) I can just give you that. \nThat's also active",
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      "content": "and those are arbitrarily cut as they don't follow our patterns",
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      "content": "but we don't know what should be there, so we can't verify design vs reality right?",
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      "content": "Peter is skeptical we can measure  - gonna go play today and see what happens",
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      "content": "I doubt even the edge from a cut that you are suggesting is clean enough to do what you hope it will. At that scale it probably looks like garbage.",
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      "content": "Looking forward to the results. Make sure Peter puts them somewhere on the internet so people can see them.",
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      "content": "thats not a thing Peter does :p",
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      "content": "Ill take a picture of the sceeen with my phone",
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      "content": "yeah there's no way it'll be clean enough for imaging, will definitely need more grinding/lapping to get past the damaged kerf zone. So you'd still need to do some detective work to figure out what part of the circuit you're looking at",
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      "content": "I should probably stop trying to solve a problem I don't have yet",
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      "content": "here's a die I cross-sectioned and lapped up to like 2000 grit iirc (something around there). Not particularly careful or good lapping, and the results are notably rough because of it. Silicon bottom, embedding epoxy top. You can see where the silicon tore out and fractured, big furrows from improper lapping through the stages, etc. \n\nStraight from a saw it'll be a nightmare mess of torn up chunks, no real chance of seeing anything interesting imo",
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      "content": "(stealth dicing might do better since it's a clean'ish break instead of saw? dunno)",
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      "content": "I have a flawed something - the only cut I have examined was bare wafer, no layers",
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      "content": "under optical -  the cut serface was mirror shiney perfect",
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      "content": "so just now I figured out the layers don't go to the edge of the die",
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      "content": "ima break a w.s die into pieces.  any suggestions on how?",
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      "content": "pinch with channel lock until it breaks into 5+ pieces.",
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      "content": "@Andrew Wingate  is the purchase slots still available to submit clean GDS for 14 July 2026?",
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      "content": "Welp, lvs hard, lvs very not optional though \ud83d\ude41",
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      "content": "No, the purchase deadline was 30 June 2026 @ 11:59 PM AoE",
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      "content": "Basically, the \"structures\" are in the very top part of the silicon - like maybe the top <5% or something.",
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      "content": "@carlfk - The Silicon Prawn Discord is probably a good source of advice / hints / etc",
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      "content": "If I can help somehow to enable functional extraction for bent-poly-on-comp, including preparing test structures necessary to verify and adjust calibration coefficients from e-test efforts, I'd like to try getting at least something functional into Run2.\n\n@Tim Edwards I'd assume the current extraction routines don't put any notable care into dealing with bent-poly-on-comp if they even support that without errors at all?",
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      "content": "@namibj :  Extraction of bent poly might differ slightly from the modeled dimensions, but I put \"reasonable\" methods into magic for dealing with bends in gates because I have several friends/colleagues who do space-qualified chips and need that extraction for annular FETs.  It will calculated the centerline through bends, ignore connecting tabs out to the edge, and if necessary, match differing lengths of segments to obtain a correct effective width.",
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      "content": "Great; if there's anything in particular I could do so we may calibrate that extraction ahead of Run3, that'd be awesome.\n\nIIUC, annular fets could maximize the gm/Cd at least at small enough diameters, compared to the classic  multi-finger structures (almost) all the open PDK PCells produce for the generic CMOS transistors?",
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      "content": "But even then, the image I replied to should already beat the classic finger structure in drain/source junction capacitance, I'd think.",
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      "content": "@namibj :  I am starting a project to make a radiation-tolerant standard cell library using annular FETs for space applications, hoping that (per recent comments on the spASICs page) there will be another opportunity to launch a properly radiation-tolerant microprocessor into space.  For now, I am targeting GF180MCU because it's the cheapest option, but I am not going to be ready to have anything on Run 2.  I expect to have something ready by Run 3.",
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      "content": "(I am also working on automating insertion of triple-voting registers into LibreLane, and if time permits, I will work on ECC for the SRAM.)",
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      "content": "Yeah I wasn't expecting something that big, just some smaller structures that could be used with a combination of extractor and model-parameter tuning, think MOSBIUS-like stuff that could be configured in different ways to exercise the transistors in many ways to gather much more broad calibration data.",
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      "content": "If you put down some test devices on Run 2 it would be very helpful.",
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      "content": "Yeah that's kind of my plan I just don't know particularly how they should look, nor what @Tim 'mithro' Ansell has in mind for how they'd need to be interfaced to get e-tested.\n\nI'll be busy catching back up with life for the next 2~4 days though, so feel free to think a bit more slowly about what'd seem like a decent idea there.\n\n(I'd also love to get shorter-channel native nmos covered if practical, as per previous discussion there are no SPICE models for the 3v3 oxide ones, and the ones for 6v0 oxide stop at fairly long channels under arguments of \"but they'd be leaky when off\", which to my understanding should be more a question of how far the gate is pulled below threshold than whether their channel dares to go below 1.8\u03bcm length.)",
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      "content": "(I do still wish to understand why the high sheet poly reistors would reasonably need a minimum 1um width; given that they are solely defined by `Poly2` drawing in a `Resistor` zone for width and the spacing of `Pplus` zones for the contacts at the ends for length; also salicide block needs to overlap the length and current density is limited, but those basically all apply on sky130 as well other than that the minimum width is about half on that.)",
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      "content": "Could be entirely because the modelling below 1um width is not precise enough.",
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      "content": "You mean they would \"need\" their spice models to have an extra bin or two for narrower resistors?",
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      "content": "I didn't check the spice models at all to see how they are made.\nBut the DRC rules from the gf180 are definitely not all \"MR\" as-in they are not all hard limits of what they can make. But with wafer.space it makes no difference, they must all be obeyed.",
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      "content": "Yeah, tbf the only real issues I have there are indeed the hard limit on min width of high sheet poly resistors `HRES.2 = 1um` and min channel length of native nmos `NAT.4 = 1.8um` especially (that's for thin oxide) but somewhat also `NAT.5 = 1.8 um` (for thick oxide), as they just state \"(For smaller `L` `Ioff` will be higher than Spec)\".\n\nBesides of course the implied impossibility of a die being designed to support both flip-chip and wire-bond packaging.",
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      "content": "putting chip chips in the sem and looking at them is fairly easy and fun....",
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      "content": "but if there is a goal, like measure pad thickness, I need to know what it is",
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      "content": "another thing I leaned: it looks like all of the layers stop before the edge.  (makes sense)",
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      "content": "what would happen if one die had one edge of layers that would get cut into so I have a well defined thing to look at?",
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      "content": "there's a risk for cracks to propagate with that; the bigger problem is likely to argue why that should pass DRC.",
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      "content": "ok, sounds reason enough.    im curious: cracks in what?  the layers I am guessing?",
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      "content": "cracks from the snapping-apart-the-silicon-wafer-along-mostly-the-dicing-cut-guiding-of-crack-propagation propagating inwards to the guard ring.",
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      "content": "I don't understand",
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      "content": "vertical cracks (the crack's plane's normal being aligned with the dicing line) propagating inwards guided by the layer interface caused by the structures you want existing.",
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      "content": "(I don't think that risk is big; but the DRCs we're subjected to are really strict.)",
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      "content": "the cutting edge \"grabbing\" the \"soft\" layers and putting unexpected force where it shouldn't be?",
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      "content": "more like, the crack in the silicon catching on it and spreading sideways along the structures.",
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      "content": "the silicon isn't sawed through; it's scratched and then snapped",
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      "content": "ah. that.  thanks.",
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      "content": "@Andrew Wingate  I wonder how our samples from Seyrecurse?  were diced",
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      "content": "this means my idea of an extra cut though some dies isn't going to help me get a clean edge to image?",
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      "content": "same way. I think you may just be thinking that because it looks shiny, it's flat. \nTo a certain extent it is, but under electron microscope it's like the Himalayas",
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      "content": "the edge of the silicon looked flat.  the layers were a mess, like cement and rebar in a demolished building",
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      "content": "that said, it shouldn't be too hard to grind/lap down from starting with sufficcient margin, and using suitable shapes visible from top for alignment.",
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      "content": "it looks like more effort than I want to put into it just for the fun of it - this is why I want a well defined goal with some value",
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      "content": "(not _easy,_ but getting down to like 50nm roughness isn't _that_ unusual for mildly fancy optical lapping)",
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      "content": "if you want to send samples, I'm happy to image them.",
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      "content": "we should have an #image channel here that I can just dump the \"this looke neet\" and \"here is 5 shots of the same thing\"",
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      "content": "IMO what might be more interesting is looking at some finer cornering/zig-zag/patterned structures on the lower layers (m1/m2 but especially also poly2 and the STI edges at comp) by lapping the BEOL gradually down",
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      "content": "I live stream of the monitor isn't out of the question.    it has even been floated to let people remotely be on speaker phone directing the SEM operator (me)",
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      "content": "this is a very cool project! Excited to see/read more when you get into it",
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      "content": "Looks like @Tim 'mithro' Ansell already gave you an answer. \nFear not! \nWe're hoping to accelerate our cadence and hope to have Run #3 with a GDS in date sometime in Dec 2026\nSo you can plan for that in the very near future!",
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      "content": "I believe @peterkinget's team might have tried it. However, wafer.space provides no type of support for this and your design must be clean by the wafer.space platform check, not whatever cadence claims.",
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      "content": "@Andrew Wingate / @Lauri - I wonder if @carlfk could take some images of bad bonds to give us more information about what is going on when they fail?",
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      "content": "https://bit.ly/test-open-pdk has the spec for pads which where used on SKY130 by @Mehdi and NIST for the data in https://github.com/google/skywater-pdk-sky130-raw-data and would probably be good to follow.",
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      "content": "I don't think I have any dies that have been tested, but I'd be happy to facilitate.",
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      "content": "One of the things we wanted to look at/confirm was the top metal thickness -- I believe we are unsure if we ended up with the 11 thousand or 9 thousand angstrom thickness for that layer.",
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      "content": "Notably I'm thinking of using structures with more than 3 pads (+substrate) involved, or at least more than 1 transistor involved, as AFAIK we do have access to model fitting tools through Sandia's Ron.",
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      "content": "For the cross sections we did of the cypress parts with @digshadow, I think the \"lapping\" was done by hand with a very fine sandpaper and that turned out pretty great. https://x.com/johndmcmaster/status/1715863105782378529?s=20",
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      "content": "Maybe coordinate with Lauri? I guess we would need to figure out how to ship the die which have not been expoxied or something?",
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      "content": "ooh.. no epoxy? Think that's necessary?",
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      "content": "It'd be important to know if we could drop to the finer pitch of layers regardless of the secondary implants for some test devices at least; think 0.28 L thick oxide structures and just-sub-1.8L nvt NMOS. And narrower-than-1.0 high sheet poly.\nI'm well aware none of those currently have SPICE models; but it's infeasible to get those SPICE model bin parameters without rather proprietary information and 3D TCAD, or by doing test structures and running model fitting on those.",
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      "content": "If that's something we'd have to prepare and submit with a replacement on hand that didn't exceed the open PDK in any way, that'd of course be fine.",
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      "content": "The epoxy isn't strictly necessary but you're going to have a much better time with it. I would recommend it if you can",
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      "content": "Oh I had cursed ideas for octagonal symmetry of a device with one drain, one source, 17 gate contacts (or 25 for symmetry, likely), and arguably 25 distinct channels in the BSIM extraction.\n\nA big part of it's usability would be contingent on the fab managing to manufacture \"decent\" matching across the (rotational) symmetry, which probably starts off mildly restrictive from the 5nm coordinate grid interacting poorly with that pesky sqrt(2) aspect, considering \"mere\" 300nm channel lengths.\n\nAlso I'm actually not _too_ sure it's appropriate to run that with the 25th channel doing anything beyond power gating, sadly.",
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      "content": "(I'm fairly confident though that structure would result in substantially lower parasitic drain side capacitance and lower excess field poly capacitance of the gate contact pads.)",
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      "content": "Ahhh ok I'll go through the links in there later; do you have any guidance on whether to expect getting finer structures (than what are almost certainly electrically motivated DRC clauses) allowed for extending the SPICE models down towards manufacturing minimums;\nin particular (unless someone tells me the FETs would be useless from short channel effects at that point):\n 1. thick oxide gates shaped like their thin oxide brethens (I'd assume they'd have substantial DIBL together short-channel-typical reduction in general threshold voltage),\n 2. native threshold voltage NMOS with lengths between normal threshold voltage minimums (0.28~0.6~0.7) and the current `NAT.4`/`NAT.5` minimum 1.8,\n 3. Un-salicided poly resistors narrower than the (I can only presume matching/process-control related) existing coded minimum widths: `PRES.1` (0.8), `LRES.1` (0.8), `HRES.2` (1.0),\n 4. `Y.PL.2` mentions 0.13 drawn channel length on thin oxide; I assume the short channel effects (possibly HCI) are generally considered too severe for other usage, but it's vendor lock to _Yield Microelectronics Corporation_ is similarly restrictive to open source EEPROM on gf18mcuD as the proprietary-core-only tiny transistors on sky130 are to _dense_ open source SRAM.\n\nLike I wish I understood better what's keeping us from being allowed marking layers to not have to bother their engineers about structures that land between electrically recommended sizing and what the lithography can manufacture without risking damage to equipment or the rest of the wafer.\n\n\nCould it be that some of this is from \"Google-sponsored-runs\" open PDK philosophy where the DRC co-writer (Google) had incentive to keep designers from submitting chips that don't work?",
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      "content": "Could you perhaps help us quantify how \"necessary\" the full guard ring structure turns out to be?\n\nI'd think we'd be able to fit some questionable guard structures along some edge that goes to the overflow zone of the reticle (the reticle seems to not be evenly divided by the slot grid along the AFAIK vertical direction of the slot size), in particular the currently forced exposure of the guard ring top metal which is very close to the wire bond pad ring's exposed top metal and not doing that would seem to allow for some cheap flip-chip options that rely on a reasonable minimum spacing between exposed top metal to not require high-end lithography to contact only one pad each.",
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      "content": "help how?  I have access to a friend's SEM, don't know much about ic design",
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      "content": "By helping us figure out what the structures would need to do/how they could be design-for-testing, so we could get that data on how critical these aspects of the guard ring are to the resulting chip yield, without the immense expense of brute force testing.\n\nI can't write much rn though.",
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      "content": "about all I have to offer: prep is tricky, it would help if the slice was at or near the edge",
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      "content": "and now is the time to add some stuff specifically for looking at when it comes back from the fab in 3 months",
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      "content": "Yeah, basically it's apparently something about cracks and potential of contaminants diffusing through a gap in a metal layer due to the dielectric filler being more vulnerable there than it would be between the vias?",
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      "content": "I'm pretty sure it'd be quite straight forward to get much of that manual stuff automated.",
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      "content": "one thing about the SEM - it takes a min or two to attach the sample to the stage (special carbon something double sided tape)   another min to load the sage into the chamber.  2 min (maybe more) to pull a vacuum.  so easy 5 min before anything shows up.",
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      "content": "I would be surprised if a sample can be removed and lapped a little more",
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      "content": "so any iteration of remove material and looking at the slice to see if it is good isn't going to happen in the SEM",
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      "content": "Yeah I know.",
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      "content": "There are a few groups from TensTorrent lurking on this Discord, maybe you can convince them to collaborate on something. I know they use ventilator internally on some stuff.",
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      "content": "(oh man, I was inches from purchasing a tenstorrent card the other day. looks like a really fun architecture to program)",
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      "content": "Howdy folks, I did a brief video of a wafer.space Tiny Tapeout chip (experimental \"ttgf0p2\") that I was lucky enough to participate in, and even luckier to try out. This is just a teaser, and I hope to share more soon: https://www.linkedin.com/posts/anton-maurovic_asic-openasics-activity-7480291900114030592-cFQw?utm_source=share&utm_medium=member_desktop&rcm=ACoAACUSJDsBhWb3XdMIrld_0q8cMtLDXdKRF8s",
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      "content": "Thanks @Tim 'mithro' Ansell for the chip! It's a beauty. And well done to the Tiny Tapeout team, of course.",
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      "content": "Hi. I\u2019m starting to work with GF PDK and was wondering about the 6V transistors and 10V LDMOS. Are they available in the shuttles?",
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      "content": "the latter aren't easy to use; the former are just longer channel vversions of the 5V types, with no real further differences besides that increased minimum channel length (and maybe a few other DRC minimums)",
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      "content": "I\u2019ve worked with LDMOS before, that\u2019s why I\u2019m interested in those. How can I enable them in the PDK, especially in KLayout?",
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      "content": "...yeah, on another matter, as you aren't the only one trying to use them, does anyone have PCells on hand for the gf180mcuD LDMOS (the 10V devices)?",
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      "content": "I see, there are not PCells available yet. That is good information, thanks!\ud83d\ude0a",
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      "content": "Alright, ya\u2019ll can have some mux4 as a treat!",
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      "content": "Now the question is how long will that take to filter through to the project template and should I rebuild TinyQV using it? TQVD is squeezed to the limit of what I can fit into it at the moment so it could help a bit.",
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      "content": "It is taking approximately three eternities to characterize, because its a 6-input function",
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      "content": "(one eternity for each process corner)",
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      "content": "I had to disable mux4_2 from synthesis, because its causing issues in timing repair",
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      "content": "I am facing this issue where the flow just gets stuck here \n\nafter the klayour-drc after the deck has finished ( the magic one ended without error) does anyone have any ides about this .\n Its been stuck there for a 1 hour now so that not supposed to happend . also checked on cpu there is no klayout running . I am on latest template .\n\nalso i want to know is it possible to restart the flow from this point if i kill it or have to run again",
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      "content": "DRC can take 3-4 hours depending on machine. If you don't have enough RAM and start swapping  that could get longer.",
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      "timestamp": "2026-07-11T13:38:39.121+00:00",
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      "content": "Question: would use of 45 degree bends of poly2 on comp have helped you on any of the cells so far?",
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      "content": "I don\u2019t think so",
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      "content": "I'll see to get the octagonal and the related quadratic structure drawn up now;\nso that I can do the write-up for them on my travel (to a meetup, in a little bit, basically as soon as I'm done with that).",
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      "content": "@Tholin note this tactic does work for gf18mcuD.",
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      "content": "The main bottleneck is actually how many metal1 traces I can have running in parallel",
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      "content": "Started a thread.",
      "author": {
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      "timestamp": "2026-07-11T21:39:10.991+00:00",
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      "content": "Does LibreLane throw any kind of error if it detects a VDD/VSS short anywhere?",
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      "content": "If it detects it ... sure. But by default the LVS is abstract so depending on where the short comes from it could be missed.",
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      "timestamp": "2026-07-11T22:12:46.186+00:00",
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      "content": "Are you worried about a chip being DOA?",
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      "content": "Sortof?",
      "author": {
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      "content": "I have the FeatherLane generated layouts on there",
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    {
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      "timestamp": "2026-07-11T22:23:06.096+00:00",
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      "content": "After determining that this issue is caused by quirks of this specific design, I\u2019m re-enabling mux4_2 for synthesis",
      "author": {
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      "timestamp": "2026-07-11T22:29:03.308+00:00",
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      "content": "I can see to get extraction running through the recently (weeks) improved magic PEX and get Xyce to solve at least DC op point for it, if you want?",
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      "content": "Yes",
      "author": {
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      "content": "(I take a `.gds`, of which I expect to have to delete all labels but the pad labels myself, followed by fully flattening it. If you have any conventions on pad labeling, I'd prefer those to be applied already and this includes separating the VDD and the VSS pads individually.)",
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      "content": "https://github.com/AvalonSemiconductors/ws-submission-2026/tree/main/FeatherLaneStuff",
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      "content": "There\u2019s two in there. Use the GDSII files. fl_mcpu32 is way smaller, test with that",
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      "content": "I'm ETA about 40 minutes from my desk.",
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      "content": "I hope `magic 8.3.674` is pretty recent?",
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      "content": "How is that to be biased/connected?",
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      "content": "Answer only needed if not obvious from looking.",
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      "content": "You can look at the .v files to see what is an input and an output",
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      "content": "If you wanna just do DC, tie all inputs low",
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      "content": "If you want to check if the outputs are outputting, you may do that.",
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      "content": "There's a series of commands in magic that will flatten the layout but ignore the text. I don't think you need to prepare a flattened version outside of magic.",
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      "content": "Oh, good; I'd need hand-holding magic just confuses me \ud83d\ude41",
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      "content": "(I'll proceed to use the same tactic as last time, provided this is with a padframe.)",
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      "content": "This magic manual page describes the 2 magic pex extraction flows. Search for `PEX` http://www.opencircuitdesign.com/magic//howto.html\n\nOne with just capacitances and one with resistors and capacitances.",
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      "content": "Ahh I'll just take only the m4 labels",
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      "content": "I got a script around that wrangles it through.",
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      "content": "```\n.subckt fl_mcpu32 VSS VDD le clk rst_n rst_override_n din[0] clk_n din[11] din[10] \n+ din[9] din[8] din[7] din[6] din[5] din[4] din[3] din[2] din[1] din[12] din[13] din[15]\n+ din[14] address[0] address[1] address[11] address[7] address[8] address[6] address[4]\n+ address[3] address[13] address[14] address[12] address[9] address[2] address[15]\n+ address[10] address[5] dout[1] dout[2] dout[3] dout[4] dout[5] dout[6] dout[7] dout[15]\n+ dout[14] dout[13] dout[12] dout[11] dout[10] dout[9] dout[8] dout[0] oeb bus_enable \n+ web unused[0] unused[1] unused[2] unused[3] unused[4] unused[5] unused[6]\n```",
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      "content": "> ```\n> Netlist error in file tb_fl_mcpu32.xyce at or near line 15\n> Model is required for device D0 and no valid model card found.\n> ```\n> great!",
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      "content": "looks like diode models need explicit importing as library....",
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      "content": "> ***** Device Count Summary ...\n>        C level 1 (Capacitor)                  280984\n>        D level 1,2 (Diode)                      9694\n>        M level 14 (BSIM4)                      44848\n>        R level 1 (Resistor)                   267528\n>        V level 1 (Independent Voltage Source)     22\n>        ---------------------------------------------\n>        Total Devices                          603076\n> ***** Setting up matrix structure...\n> ***** Number of Unknowns = 292543\n> ***** Initializing...\n> \n> \n> Analyzed Singleton Problem:\n> ---------------------------\n> Singletons Detected!\n> Num Singletons:      44\n> ---------------------------\n> \n> \n> ConstructedSingleton Problem:\n> ---------------------------\n> RatioOfDimensions:   0.99985\n> RatioOfNonzeros:     0.765899\n> ---------------------------\n> \n> ZOLTAN Load balancing method = 10 (HYPERGRAPH)",
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      "content": "(that's the small one; the large one is still extracting)",
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      "content": "Oh, so that\u2019s what that happens! I usually just remove the diodes from the netlist.",
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      "timestamp": "2026-07-12T00:29:27.075+00:00",
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      "content": "(Yeah it's LLM-prepared; minor manual edits have been done to it; nothing about this testbench seemed too complex to be likely to break and it's hot here... really hot, for 2:30 am.)",
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      "content": "mayhaps continuation=2 (natural MOS parameter homotopy) was not the efficcient thing to do, for as it's still stuck on the same screen/output as shown above.)",
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      "content": "let's try without continuation and to directly solve for the 3.3V case.",
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      "content": "(affording the 2.5 + 1.7 GB of ram usage for the continuation attempt, I've paused that and am trying now without continuation.)",
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      "content": "(maybe full-die PEX usage is actually only for cluster usage... hmmmpf)",
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      "content": "Started a thread.",
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      "content": "There is no need to to PEX ...",
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      "content": "You can instruct librelane to use GDS for LVS instead of DEF and then the LVS will actually check submodules instead of abstracting then. And you can double check that in the report.",
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      "content": "https://discord.com/channels/1361349522684510449/1523053835864637510/1524075766219014326\n\n@RebelMike is the free edge possibly free of top metal, and as such possibly suited for putting flip chip bond pads there?",
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      "content": "metal5 is used for power rails, so there's probably not loads of space.  But if you want to try and prove some flip chip bonding method maybe it would be better to make a test project where you didn't need most of the pads to work in order to get anything useful out?  If Tim thinks that is an interesting project it might get accepted by the sounds of things",
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      "content": "Yeah so, the thing is, most of the chip would be barren if only housing connectivity (4-wire kelvin measurements) test pads.\nAnd in this time I can't get much interesting structure done below, sadly, especially given that I'm not allowed to test vaguely-short channel native nfet's because someone decided years ago what amount of subthreshold leakage would be permissible to design with, and banned all channels narrower than that.\nThough I guess I should check again if the 0.5um channels would pass DRC.",
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      "content": "Oh I see now.\nWould that chip need more than one VDD/VSS pair per SRAM tile?\n\nEven if, feeding the m4 straps both at the bottom and the top of each tile (or like, connecting the m4 through and putting a shared m5 connection at the border between SRAM tiles, freeing up m5 over the active memory region), that would give plenty of freedom for some varied pad designs.\n\nAlso would conveniently test \"circuit under [flip-chip] pad\".",
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      "content": "How fast are the available IO pins? The possibility of free silicon is almost irresistable but I think the best path I'd have to doing something relatively cool would be to use my ethernet library. Unfortunately I only have RGMII support, so i'd need 125MHz IO \ud83e\udd14",
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      "content": "Feeding power to those SRAMs is a bit tricky as they ideally need connections around their edges.  I'm in the final stages of finishing this design so don't really want to be messing with things, but I'm not paying for it so if Tim/Leo would like to dedicate some area to a flip chip pin test I could potentially just remove some of the SRAMs if you had a macro that would drop in their place.  I'm pretty sure the PDN grid will just drop some straps if you block met5, which maybe isn't ideal for power distribution integrity, but probably also not a disaster.\n\nAnd if you had a ready to go macro i would also be easy for someone to drop into a different design.",
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      "content": "I mean in principle the edges would be free? The wiring would ideally be escaped somehow to an e.g. ESD diode or something.",
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      "content": "That should work.",
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      "content": "Re: ready-to-go macro: basically I'm hoping to test a few mostly pairs of pads of sufficciently varied size and pitch, primarily targeting the \"ACF + JLC's special 2L 0.33oz (each) flex\" affordable baseline.",
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      "content": "I think the best answer we have is: probably.  A 200MHz input clock worked ok.  The outputs are strong so likely to work at that speed, but as far as I know I don't think anyone has tried anything non-trivial running at a fast clock in run 1.",
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      "content": "Yeah not sure how fast the 3v3 library is in practice, but the foundry 5V library even the 9T one is apparently fairly slow.",
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      "content": "Cool, I might give this project a shot then \ud83e\udd14",
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      "content": "Indeed - the challenge will likely be more in driving the logic that fast, not the speed of the IO pads",
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      "content": "IMO prepare to immediately put a DDR serdes by the IO pads without much routing, drop down to at least 4 if not 8 wide per-IO-lane; then your core should likely have no severe issues synthesizing to timing.",
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      "content": "@RebelMike For the record, a major practical use case I'm hoping to prove viable with this is putting more than one flip chip pad on a standard-size TT analog tile, i.e., on that 340x325um area, and in  a way that can be extended sideways to cover up to maximum-size analog tile.\n\nSo we're not talking about large areas here, for the most part at least.",
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      "content": "I think this is my most scuffed tapeout so far, seeing as I have to make manual edits in KLayout to the top-level GDSII to fix DRC errors.",
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